发明名称 |
METHOD AND DEVICE FOR HIGH-LEVEL SYNTHESIS |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for high-level synthesis that can select a memory of an optimum bit width depending upon an operation described in an operation level circuit and optimize the number of cycles of memory accesses, and to provide a device therefor. SOLUTION: The frequency of a reference to a variable described in the operation level circuit is calculated first. Then the bit width of the variable is extracted and a plurality of memories capable of data transfer of the extracted bit width are selected. Further, the total of the numbers of cycles of memory access when the variable is allocated is calculated on the basis of the frequency of the reference and the bit width of the variable. Then, the memory having the smallest total of the calculated numbers of cycles is selected as an object of variable allocation. COPYRIGHT: (C)2005,JPO&NCIPI
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申请公布号 |
JP2005173648(A) |
申请公布日期 |
2005.06.30 |
申请号 |
JP20030408223 |
申请日期 |
2003.12.05 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
HATTORI MASARU;KUROKAWA KEIICHI;OGAWA OSAMU |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
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