发明名称 |
On-chip serialized peripheral bus system and operating method thereof |
摘要 |
Provided is an on-chip serialized peripheral bus system and method of operating the same, wherein when a plurality of low-speed peripherals are connected to a system that employs a high-speed parallel bus, the existing parallel bus system for connecting the low-speed peripheral becomes serialized, thereby reducing a bus width of the parallel bus as well as improving a connection response time of the low-speed peripheral, and reducing a simultaneous transition frequency of the peripheral connection bus system to improve the performance of the overall system.
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申请公布号 |
US2005144331(A1) |
申请公布日期 |
2005.06.30 |
申请号 |
US20040913418 |
申请日期 |
2004.08.09 |
申请人 |
KIM YOUNG W.;KIM SUNG N.;KIM SUN W.;PARK KYOUNG;KIM MYUNG J. |
发明人 |
KIM YOUNG W.;KIM SUNG N.;KIM SUN W.;PARK KYOUNG;KIM MYUNG J. |
分类号 |
G06F3/00;G06F13/00;(IPC1-7):G06F3/00 |
主分类号 |
G06F3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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