DELTA-SIGMA TYPE FRACTION DIVISION PLL SYNTHESIZER

摘要

It is possible to obtain a low spurious of a delta-sigma type fraction division PLL synthesizer. The delta-sigma type fraction division PLL synthesizer includes a first and a second L-value accumulator (31, 30), and an adder (29) for calculating a difference of overflow signals (16, 17) of the first and the second L-value accumulator (31, 30), so that the output of the adder (29) switches the division ratio of a variable divider (2) having a division ratio which can be switched to M, M+1, M-1. Thus, frequency of spurious generated by an operation noise of the first and the second L-value accumulator (31, 30) is shifted to a higher frequency component than the prior art and removed by a loop filter (low pass filter) (5).