| 摘要 |
<P>PROBLEM TO BE SOLVED: To lower a danger where damage in dicing reaches a chip area and to prevent a decrease of reliability of a semiconductor device. <P>SOLUTION: A multi-layer structure of inter layer insulating films 105 to 109 is formed on a substrate 101. Wiring 112, 114, 116 are formed on the inter layer insulating films 105 to 109 of the chip area 102 and via holes 111, 113, 115 are formed on them too. In the multi-layer structure of the inter layer insulating films 105 to 109 in the surrounding portion of the chip area 102, a seal ring 104 penetrating the multi-layer structure and continually surrounding the chip area 102 is formed. A seal via hole 123 having no joint is located in the inter layer insulating film 107 where the via hole 113 and the wiring 114 compose the dual damascene wiring. The passivation film 109 of an upper portion of the multi-layer structure of the inter layer insulating films 105 to 109 has an opening on the seal ring 104 and a cap layer 125 connecting with the seal ring 104 is formed on the opening. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
