发明名称 RESISTANCE ADJUSTMENT CIRCUIT AND MATRIX TYPE DISPLAY DEVICE USING THE SAME
摘要 PROBLEM TO BE SOLVED: To suppress the degradation in a display grade due to separation lines by suppressing the difference in resistance by each of wiring for scanning signal lines of a display panel used in a display device. SOLUTION: A resistance adjustment circuit 1 using a potentiometer 21 (a resistance selection circuit) is built in between a voltage source 5 and a gate driver 6. The value of the resistance for adjustment is previously set in the potentiometer 21 from the outside by each of the scanning signal lines determined from a gate start pulse GSP and a clock for the gate driver. Also, a counter 22 for transmitting the selection timing of the respective scanning signal lines to the potentiometer 21 by counting the gate clock is disposed. A gate on voltage GOE is inputted from the voltage source 5 to the input side of the potentiometer 21 and single wiring on the input side of the gate driver 6 is connected to the output side. The respective scanning signal lines GL 1, GL 2, etc., GLn are emerged from the output side of the gate driver 6. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005165034(A) 申请公布日期 2005.06.23
申请号 JP20030404814 申请日期 2003.12.03
申请人 SHARP CORP 发明人 YAMAGUCHI AKIRA
分类号 G02F1/133;G09G3/20;G09G3/36;(IPC1-7):G09G3/36 主分类号 G02F1/133
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