| 摘要 |
PROBLEM TO BE SOLVED: To provide a device and a method for designing a semiconductor integrated circuit capable of meeting timing restrictions without disposing BFBs (BuFfer Blocks), and of enhancing convergence for optimization. SOLUTION: An automatic LSI design simulator 10 determines the number of clocks used in a clock generating function part 30 and a clock delay for each clock, allocates the clocks constituting a clock system, and verifies constraints to design on the basis of each clock. A tree determining function part 32 uses the generated clock system, adjusts the skew of each clock, adjusts the delay of each clock, verifies layout adjustments, and takes in supplied data without violating the timing restrictions, so as to enhance convergence that meets all the timing restrictions. COPYRIGHT: (C)2005,JPO&NCIPI
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