| 摘要 |
PROBLEM TO BE SOLVED: To provide an asynchronous signal input apparatus capable of rapidly converging the phase difference between data read from FIFO for input data delivery and data written into the FIFO into a target phase difference, and maintaining a convergence status, and to provide a sampling frequency converting apparatus using the apparatus. SOLUTION: A phase lock determining circuit 51 monitors a data accumulating amountΔS in an FIFO 10 supplied from an up-down counter 50. If thisΔS value is within a target range for a predetermined time or more, the circuit 51 determines that a PLL 80 is phase-locked, lowers a loop gain of the PLL 80, and instructs a converting section 61 of a loop filter section 60 to use a conversion table for suppressing the change in frequency of a reading clock CKR to be outputted from a variable frequency oscillation section 70. On the contrary, if it is determined that theΔS is out of the target value, the conversion table of rapidly phase-locking the PLL 80 is selected. COPYRIGHT: (C)2005,JPO&NCIPI
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