发明名称 Method for identifying basic blocks with conditional delay slot instructions
摘要 A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages to determine which instructions to cancel. The assignment of tags for a fetch group of concurrently fetched instructions may be performed in parallel. A plurality of branch sequence numbers may be generated, and one of the plurality may be selected for each instruction responsive to the cumulative number of branch instructions preceding that instruction within the fetch group. The selection may be further responsive to whether or not the instruction is in a conditional delay slot.
申请公布号 US2005132176(A1) 申请公布日期 2005.06.16
申请号 US20050046439 申请日期 2005.01.28
申请人 KRUCKEMYER DAVID A. 发明人 KRUCKEMYER DAVID A.
分类号 G06F9/38;(IPC1-7):G06F15/00 主分类号 G06F9/38
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