| 摘要 |
In an operation to supply an input signal IN having an amplitude equal to a first power-supply voltage VDD 1 to the gate of a PMOS transistor PM 51 operating at a second power-supply voltage VDD 2 higher than the first power-supply voltage VDD 1 , the levels of signals are converted by using PMOS transistors PM 1 to PM 4 . The sources of the PMOS transistors PM 1 and PM 3 are connected to a line of the first power-supply voltage VDD 1 whereas the sources of the PMOS transistors PM 2 and PM 4 are connected to a line of the second power-supply voltage VDD 2 . The gate of the PMOS transistor PM 4 is connected to the drains of the PMOS transistors PM 1 and PM 2 . The gate of the PMOS transistor PM 2 is connected to the drains of the PMOS transistors PM 3 and PM 4 . An inverted signal of the input signal IN is supplied to the gate of the PMOS transistor PM 1 and the input signal IN is supplied to the gate of the PMOS transistor PM 2 . The amplitude of the input signal IN is converted from a magnitude equal to a difference between a reference signal VSS and the first power-supply voltage VDD 1 into a magnitude equal to a difference between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 . A signal obtained as a result of the conversion is output from the PMOS transistors PM 1 and PM 2 , being used for controlling electrical conduction of a PMOS transistor PM 51.
|
