发明名称 Integrated logic circuit and hierarchical design method thereof
摘要 Modules 14 to 18 are disposed in a chip 10 , and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14 , and an internal circuit 21 disposed inside the plurality of external buffer cells 20 . Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20 . The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21 . The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.
申请公布号 US2005128850(A1) 申请公布日期 2005.06.16
申请号 US20050042061 申请日期 2005.01.26
申请人 FUJITSU LIMITED 发明人 SUZUKI KENJI;OSAJIMA TORU;TAJIMA SHOGO;SATOH SHIGENOBU
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;H03K19/177;(IPC1-7):G11C7/00 主分类号 G06F17/50
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