发明名称 REFRESH CONTROL SYSTEM OF SEMICONDUCTOR MEMORY APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus in which refresh operation of a second time is performed for a memory cell existing in the same memory sub-array which is different from a memory cell refreshed by refresh operation of a first time. SOLUTION: This apparatus is provided with a pair of memory sub-array, and a control signal generating circuit outputting first and second refresh start signals in order within an operation time of an external refresh command responding to an internal refresh command. The memory sub-array has a plurality of memory cells sharing a sense amplifier and connected to each bit line and word line and arranged in a matrix type. Responding to the first refresh start signal, the first refresh operation is performed for a memory cell group connected to one side of the first word line out of the memory sub-array, responding to the second refresh start signal, the second refresh operation is performed for a memory cell group connected to the second word line being different from one side of the first word line. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005158158(A) 申请公布日期 2005.06.16
申请号 JP20030395837 申请日期 2003.11.26
申请人 ELPIDA MEMORY INC 发明人 DONO CHIAKI;KOSHIKAWA KOJI
分类号 G11C11/406;G11C11/407;G11C29/00;(IPC1-7):G11C11/406 主分类号 G11C11/406
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