发明名称 |
Offset spacer process for forming N-type transistors |
摘要 |
A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with Arsenic (As) diffusion on strained semiconductor layers. The process can be utilized for SMOS metal oxide semiconductor field effect transistors (MOSFETs). The strained layer can be a strained silicon layer formed above a germanium layer.
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申请公布号 |
US6905923(B1) |
申请公布日期 |
2005.06.14 |
申请号 |
US20030619877 |
申请日期 |
2003.07.15 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
PATON ERIC N.;WANG HAIHONG;XIANG QI |
分类号 |
H01L21/8238;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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