发明名称 |
DIGITAL SIGNAL PROCESSOR ARCHITECTURE WITH OPTIMIZED MEMORY ACCESS |
摘要 |
A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code discontinuity is encountered, the unified memory is accessed a first time during an instruction cycle with a dummy access. The unified memory is accessed a second time during the instruction cycle when a program code discontinuity is encountered with either a data access, as in the case of a last instruction of a loop, or an instruction access, as in the case of a jump instruction. |
申请公布号 |
WO2005052788(A1) |
申请公布日期 |
2005.06.09 |
申请号 |
WO2004US34291 |
申请日期 |
2004.10.18 |
申请人 |
ANALOG DEVICES, INC.;BOUTAUD, FREDERIC |
发明人 |
BOUTAUD, FREDERIC |
分类号 |
G06F9/30;G06F9/312;G06F9/318;G06F9/32;G06F9/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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