| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To match the delay of a feedback passage accurately to the delay from an external terminal for clock input to an external terminal for clock output. <P>SOLUTION: A semiconductor chip (11) has a plurality of pad electrodes (13A, etc), and a mounting circuit section (10) has wiring for connecting with the pad electrodes of the semiconductor chip, mounting terminals (14A, etc), and a first signal passage (FBR 2) for receiving a signal outputted from a predetermined pad electrode and transmitting the signal to other pad electrode. In a second signal passage from a predetermined mounting terminal (14D) through the semiconductor chip to other mounting terminal (14H), the first signal passage has a delay element comparable to a delay of a first partial passage from the predetermined mounting terminal to the input pad electrode of the semiconductor chip, and a delay of a second partial passage from the output pad electrode of the semiconductor chip to other mounting terminal, and it is arranged in a phase comparison feedback passage for synchronizing the phase of an output signal from the second signal passage with the phase of an input signal to the second signal passage. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
