发明名称 |
Floating point multiplier/accumulator with reduced latency and method thereof |
摘要 |
A circuit ( 10 ) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from a critical speed path for dependent calculations. An intermediate representation of a product and a third operand are selectively shifted to facilitate use of prior unnormalized dependent resultants. Logic circuitry ( 24, 42 ) implements a truth table for determining when and how much shifting should be made to intermediate values based upon a resultant of a previous calculation, upon exponents of current operands and an exponent of a previous resultant operand. Normalization and rounding may be subsequently implemented, but at a time when a new cycle operation is not dependent on such operations even if data dependencies exist.
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申请公布号 |
US6904446(B2) |
申请公布日期 |
2005.06.07 |
申请号 |
US20010939244 |
申请日期 |
2001.08.24 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
DIBRINO MICHAEL |
分类号 |
G06F7/544;(IPC1-7):G06F7/38 |
主分类号 |
G06F7/544 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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