发明名称 |
Architecture for circuit connection of a vertical transistor |
摘要 |
An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region. In another embodiment a first device region, is formed on a semiconductor layer. A second device region, is also formed on the semiconductor layer. A conductor layer comprising metal is positioned adjacent the first and second device regions to effect electrical connection between the first and second device regions. A first field effect transistor gate region is formed over the first device region and the conductor layer and a second field effect transistor gate region is formed over the second device region and the conductor layer.
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申请公布号 |
US6903411(B1) |
申请公布日期 |
2005.06.07 |
申请号 |
US20000648164 |
申请日期 |
2000.08.25 |
申请人 |
AGERE SYSTEMS INC. |
发明人 |
CHYAN YIH-FENG;HERGENROTHER JOHN MICHAEL;MONROE DONALD PAUL |
分类号 |
H01L27/10;H01L21/336;H01L21/768;H01L21/8234;H01L21/8238;H01L21/8244;H01L27/092;H01L27/11;H01L29/78;(IPC1-7):H01L29/778 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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