| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL clock signal generation circuit capable of maintaining a proper locked status even when the operation region of a voltage controlled oscillator is narrow. <P>SOLUTION: The PLL clock signal generation circuit comprises a phase comparator 101, a charge pump circuit 102, a filter circuit 103, a voltage controlled oscillator 104, and frequency dividers 105 and 106. The PLL clock signal generation circuit is further provided with a multiplication rate control circuit 107, which detects a state of a reference voltage output from a filter circuit 103 and controls change of the multiplication rate of the frequency dividers according to a detection result. The multiplication rate control circuit 107 detects if the operation of the PLL clock signal generation circuit deviates from a lockable region by detecting the state of the reference voltage, and outputs a control signal LPFOUT for changing the multiplication rate so that the operation of the PLL clock signal generation circuit does not deviate from the lockable region. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
