发明名称 Bias voltage generator circuit
摘要 A bias voltage generator circuit capable of keeping a constant electric current consumption (I<SUB>0</SUB>) and supplying bias voltages (V<SUB>1</SUB>, V<SUB>2</SUB>) respectively kept at constant values relative to its source voltage (V<SUB>DD</SUB>) and GND potential even when V<SUB>DD </SUB>fluctuates. The circuit includes: three p-channel transistors connected in a current mirror, each having a source connected to source voltage; and four n-channel transistors, each having a source connected to GND. Bias voltages V<SUB>1 </SUB>and V<SUB>2 </SUB>are in a relation such that they control each other. Concretely, the V<SUB>1 </SUB>potential starting to rise causes the V<SUB>2 </SUB>potential to start to decrease, and the V<SUB>1 </SUB>potential starting to decrease causes the V<SUB>2 </SUB>potential to start to rise. The circuit has the property of making the circuit current fixed regardless of V<SUB>DD</SUB>. Even when V<SUB>DD </SUB>fluctuates, I<SUB>0 </SUB>is constant and V<SUB>1 </SUB>and V<SUB>2 </SUB>each produce a fixed potential.
申请公布号 US2005116766(A1) 申请公布日期 2005.06.02
申请号 US20040999179 申请日期 2004.11.29
申请人 WATANABE SHINICHI 发明人 WATANABE SHINICHI
分类号 H01L27/04;G05F1/10;G05F3/20;G05F3/24;G05F3/26;H01L21/822;H03F1/30;H03F3/345;(IPC1-7):G05F1/10 主分类号 H01L27/04
代理机构 代理人
主权项
地址