| 摘要 |
A multi-bus I<SUP>2</SUP>C (inter integrated circuit) system includes an 1<SUP>2</SUP>C controller ( 100 ), a CPU ( 200 ), an I<SUP>2</SUP>C bus ( 300 ), a decoder circuit ( 400 ), and eight I<SUP>2</SUP>C buses ( 510 - 580 ). The decoder circuit ( 400 ) of the multi-bus I<SUP>2</SUP>C system includes a binary decoder ( 410 ), a latch buffer ( 420 ), eight NOT gates ( 431 - 438 ), and eight NAND gates ( 441 - 448 ). The binary decoder ( 410 ) of the decoder circuit ( 400 ) is a 3-to-8 decoder. The multi-bus I<SUP>2</SUP>C system can include any number of I<SUP>2</SUP>C buses according to particular requirements. In such cases, the binary decoder ( 410 ) of the multi-bus I<SUP>2</SUP>C system has the required number of input ports and output ports. For example, the binary decoder ( 410 ) can be a 4-to-16 decoder.
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