| 摘要 |
A thin film integrated multilayer capacitor with substantially enhanced capacitance density suitable for Dynamic Random Access Memory (DRAM) and other integrated capacitor applications is formed into a trench or cavity structure with a completely self-aligned atomic layer deposition (ALD) process flow. Each conductor layer is etched with a wet etch to create recesses between the adjacent insulating layers, which recesses are seamlessly filled with dielectric using an ALD process, so that no part of the conductor is ever exposed to ambient atmosphere. Only silicon-based dielectric materials contact the silicon substrate, and the contact area between silicon and the capacitor is minimized both at the top and the bottom. The dielectric layers comprise Al<SUB>2</SUB>O<SUB>3</SUB>, ZrO<SUB>2</SUB>, or HfO<SUB>2</SUB>, which is deposited using an ALD process. Capacitance density is greatly enhanced to a C/∈ of above 1500 fF/mu<SUP>2</SUP>.
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