发明名称 |
Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation |
摘要 |
Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.
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申请公布号 |
US6898139(B2) |
申请公布日期 |
2005.05.24 |
申请号 |
US20040773024 |
申请日期 |
2004.02.05 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE JAE-WOONG;KIM CHI-WOOK;KANG SANG-SEOK |
分类号 |
G11C11/40;G11C7/10;G11C7/22;G11C29/14;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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