Microcontroller for time-controlled bus system has interrupt processing unit between interrupt source interface and CPU that processes incoming interrupts and stores them in interrupt memory

摘要

The device has a CPU (2)with associated dispatcher, a program memory, a working memory, an interface to a protocol controller for the bus system and at least one interface to an interrupt source (9-12). An interrupt processing unit (7) is arranged between the interrupt source interface and the CPU, whereby the interrupt processing unit has at least one CPU (14), program memory (16), working memory (17) and interrupt memory (18). Incoming interrupts are processed by the interrupt processing unit and stored in the interrupt memory.