发明名称 Serial transistor-cell array architecture
摘要 A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. Unique sensing techniques are provided to sense the states of the storage elements. The logical states of the storage elements are decoupled from one another and are read independently.
申请公布号 US2005105329(A1) 申请公布日期 2005.05.19
申请号 US20040873112 申请日期 2004.06.23
申请人 NAZARIAN HAGOP A. 发明人 NAZARIAN HAGOP A.
分类号 G11C11/00;G11C11/16;G11C13/00;G11C13/02;G11C16/02;G11C16/26;G11C27/00;(IPC1-7):G11C11/00 主分类号 G11C11/00
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