发明名称 |
Pattern recognition in an integrated circuit design |
摘要 |
A method for recognizing a pattern in a design of an integrated circuit (IC), comprising identifying a pattern correspondence element in a pattern instance. A pattern tree corresponding to the pattern instance is built. A list of candidate design correspondence elements in a design instance of the IC are built. Iteratively, for each design correspondence element in said list of candidate design correspondence elements each rank in a tree representation of said design instance built around said each design correspondence element is compared with corresponding rank in said pattern tree.
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申请公布号 |
US2005108675(A1) |
申请公布日期 |
2005.05.19 |
申请号 |
US20040783091 |
申请日期 |
2004.02.23 |
申请人 |
ATRENTA, INC. |
发明人 |
MURPHY BERNARD;PRASOON PRATYUSH K.;BHATIA MANISH |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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