发明名称 |
SCHALTUNGSANORDNUNG UND VERFAHREN ZUM DETEKTIEREN EINES UNERWÜNSCHTEN ANGRIFFS AUF EINE INTEGRIERTE SCHALTUNG |
摘要 |
A circuit configuration for detecting an unwanted attack on an integrated circuit has a signal line to which a clock signal is applied and at least one line pair which is respectively used to code a bit. The signal line and the at least one line pair are connected between a first and a second circuit block in the integrated circuit. The signal line and the at least one line pair are connected to a detector circuit which changes the operating sequence in the integrated circuit on the basis of the signals on the signal line and on the at least one line pair. The detector circuit can be used to the same extent to test for production faults. |
申请公布号 |
AT293806(T) |
申请公布日期 |
2005.05.15 |
申请号 |
AT20010967051T |
申请日期 |
2001.08.30 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
GAMMEL, BERNDT |
分类号 |
G01R31/317;G06F1/00;G06F12/14;G06F21/75;H01L21/822;H01L23/58;H01L27/04;(IPC1-7):G06F1/00 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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