| 摘要 |
PROBLEM TO BE SOLVED: To provide a transistor wherein the upper and lower gate electrodes are positionally aligned with each other so that the short channel effect is suppressed, and also to provide a method for manufacturing the same. SOLUTION: An SOI substrate is used, wherein a buried insulating layer 101 and a single-crystal silicon layer 102 are deposited on a supporting board 100. An upper gate insulating film 107, a polysilicon film 108 to be the upper gate electrode 130a, and an SiN film 109 are formed on them. An impurity is introduced into the single-crystal silicon layer 102 and then etching is performed for the single-crystal silicon layer 102. A lower gate insulating film 118 is then formed on the lower surface of the single-crystal silicon layer 102. Recesses are formed on both sides of the single-crystal silicon layer 102, a continuous hole is formed under them, and they are filled with polysilicon. Next, the polysilicon is etched for the formation of a polysilicon film to be the lower gate electrode. COPYRIGHT: (C)2005,JPO&NCIPI
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