发明名称 Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation
摘要 A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a priority higher than the interrupt priority value, priority inversion can be avoided. Switching to the same thread before any interrupt servicing, and disabling interrupts and thread switching during interrupt servicing can simplify the interrupt handling logic. By storing trap background data for traps and servicing traps only in their originating threads, trap traceability can be preserved. By disabling interrupts and thread switching during trap servicing, unintended trap re-entrancy and servicing disruption can be prevented.
申请公布号 US2005102458(A1) 申请公布日期 2005.05.12
申请号 US20030712473 申请日期 2003.11.12
申请人 INFINEON TECHNOLOGIES NORTH AMERICA CORP. 发明人 OBER ROBERT E.;ARNOLD ROGER D.;MARTIN DANIEL F.;NORDEN ERIK K.
分类号 G06F9/46;G06F9/48;(IPC1-7):G06F13/24 主分类号 G06F9/46
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