Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout

摘要

A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.