发明名称 |
Adding circuit suitable for sigma-delta modulator circuits |
摘要 |
An adding circuit is disclosed. The adding circuit includes storage capacitors and switching or switching means, the storage capacitors being charged up via voltage signals to be added during a first clock phase. During a second clock phase, the storage capacitors are connected in parallel, with the result that a charge equalization occurs. After the charge equalization, the voltage dropped across the parallel-connected storage capacitors is equal to a sum of the signals to be added except for a scaling factor. In one embodiment, the adding circuit is used in a sigma-delta modulator circuit.
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申请公布号 |
US2005093728(A1) |
申请公布日期 |
2005.05.05 |
申请号 |
US20040935675 |
申请日期 |
2004.09.02 |
申请人 |
GAGGL RICHARD;INVERSI MAURIZIO;WIESBAUER ANDREAS |
发明人 |
GAGGL RICHARD;INVERSI MAURIZIO;WIESBAUER ANDREAS |
分类号 |
G06F7/50;H03K5/00;H03K5/24;H03K7/00;H03M3/00;H03M3/02;(IPC1-7):H03M3/00 |
主分类号 |
G06F7/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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