| 摘要 |
A data output control circuit for use in a synchronous semiconductor memory device including: a first data output enable signal generation unit for receiving an internal signal and generating a rising data output enable signal synchronizing with a rising edge of a DLL clock signal according to a CAS latency; and a second data output enable signal generation unit for receiving the rising data output enable signal and generating a falling data output enable signal synchronizing with a falling edge of the DLL clock signal.
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