| 摘要 |
A method of fabricating a semiconductor device, including at least the steps of (a) forming a via-hole or trench throughout an electrically insulating layer, (b) forming a wiring material layer on the electrically insulating layer such that the via-hole or trench is filled with the wiring material layer, (c) annealing the wiring material layer, (d) cooling the wiring material layer down to a temperature equal to or lower than a predetermined temperature, and (e) applying chemical mechanical polishing (CMP) to the wiring material layer such that the wiring material layer exists only in the via-hole or trench. The step (c) is carried out prior to the step (e), and the step (d) is carried out after the step (c).
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