摘要 |
A chain of processing element (l0a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic circuit (14) of a next processing element (10a, 10, l 0b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (l0b) includes loading time points of loading all processing elements (l0a, 10) other than the final processing element (10). |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;PEETERS, ADRIANUS, M., G.;VAN BERKEL, CORNELIS, H.;DE CLERCQ, MARK, N., O. |
发明人 |
PEETERS, ADRIANUS, M., G.;VAN BERKEL, CORNELIS, H.;DE CLERCQ, MARK, N., O. |