| 摘要 |
PROBLEM TO BE SOLVED: To generate a bias voltage wherein spurious frequency components are sufficiently reduced, while suppressing the expansion of an occupied area on a semiconductor chip. SOLUTION: The bias circuit is provided with: a PLL circuit 117 for generating a regulated bias voltage 107; a gm amplifier 109 for outputting a current based on a DC voltage 108 and the bias voltage 107; a gm amplifier 110 for outputting a current based on the DC voltage 108 and a bias voltage 116; and an integration circuit 118 for integrating the difference between the output currents of the gm amplifiers 109, 110 to output the bias voltage 116. COPYRIGHT: (C)2005,JPO&NCIPI
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