DIGITAL CIRCUIT HAVING A DELAY CIRCUIT FOR CLOCK SIGNAL TIMING ADJUSTMENT

摘要

A digital circuit has a pulse delay circuit that is designed such that a drive current for an inverter is variable so as to provide variable timing of clock signals. The pulse delay circuit includes a circuit for stabilizing the pulse delay amount by use of a delay synchronization loop, and also includes a circuit for generating a pulse delay amount setting voltage that has a nonlinear characteristic. The present invention can realize a timing delay circuit that is small in area, not affected by operational environment and exhibits a high resolution.