Analog to digital converter with bandwidth tuning circuit

摘要

A pipelined analog to digital converter. Each stage in the pipeline has a flash converter and a multiplying digital to analog converter. Each stage provides a digital bits and an analog residue that is passed to the next stage in the pipeline. The digital bits from all stages are combined in digital logic to produce the digital output of the converter. The flash converter in each stage has a set of comparators, each coupled to a reference ladder. A random number generator in connection with a switch matrix "shuffles" the reference inputs to the comparators. The comparators are latched as soon as practical after they are stable and the reference inputs are shuffled as soon as practical after the comparators are latched. Also, a bandwidth trim circuit is provided to compensate for different cutoff frequencies of the input impedances of the flash and multiplying digital to analog converters.