| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including voltage supply wiring without increasing chip costs. <P>SOLUTION: In the semiconductor device comprising a memory cell array wherein a plurality of main body cells and a plurality of dummy cells provided for absorbing the influence of variations in the working dimension of the main body cells are formed, each main body cell includes a main body transistor 19 and main body wiring 6, 7, 8, 13 electrically connected with the main body transistor 19, and each dummy cell includes dummy transistors 83, 84 and dummy wiring 5, 11 electrically connected with the dummy transistors 83, 84, the dummy wiring 5, 11 being electrically connected with the main body wiring 6, 7, 8, 13 to supply an applied predetermined bias voltage to the main body transistors 19 included in the main body cells. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
