| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To solve the problem wherein undesired clock is generated at the waiting of oscillation stability of sleep restoration. <P>SOLUTION: A source clock clk-org is inputted to a frequency divider 102 in a frequency divider circuit 101, clocks clk0-org and clk1-org of the desired frequencies are generated, an oscillation stability wait control signal okclk is inputted to the input of a flip-flop 105 for oscillation stability wait release signal control in an oscillation stability wait circuit 104 for source clock control, Low is inputted to a load hold signal okclklh, and a clock stopping circuit 106 releases clock stopping, on the basis of an output okclkmode of the flip-flop 105 for oscillation stability wait release signal control. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
