发明名称 |
Method and apparatus for coherent memory structure of heterogeneous processor systems |
摘要 |
Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.
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申请公布号 |
US2005080998(A1) |
申请公布日期 |
2005.04.14 |
申请号 |
US20030682386 |
申请日期 |
2003.10.09 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DAY MICHAEL NORMAN;HOFSTEE HARM PETER;JOHNS CHARLES RAY;KAHLE JAMES ALLAN;SHIPPY DAVID J.;TRUONG THUONG QUANG |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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