发明名称 |
System and method for data synchronization for a computer architecture for broadband networks |
摘要 |
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.
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申请公布号 |
US2005081209(A1) |
申请公布日期 |
2005.04.14 |
申请号 |
US20040967433 |
申请日期 |
2004.10.18 |
申请人 |
SONY COMPUTER ENTERTAINMENT INC. |
发明人 |
SUZUOKI MASAKAZU;YAMAZAKI TAKESHI |
分类号 |
G06F12/14;G06F15/16;G06F15/80;G06F21/24;H04L29/06;(IPC1-7):G06F9/46 |
主分类号 |
G06F12/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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