发明名称 Method and apparatus for a chaotic computing module
摘要 A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. The logic gate can operate as one of a plurality of different logic gates responsive to adjusting at least one of the threshold reference signals.
申请公布号 US2005073337(A1) 申请公布日期 2005.04.07
申请号 US20030680271 申请日期 2003.10.07
申请人 UNIVERSITY OF FLORIDA 发明人 DITTO WILLIAM L.;MURALI KRISHNAMURTHY;SINHA SUDESHNA
分类号 G06F;G06F7/38;G06F17/50;G06G7/00;G06G7/38;G06N7/08;H03K17/693;H03K19/173;(IPC1-7):G06F17/50 主分类号 G06F
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