发明名称 Feeble signal extracting circuit
摘要 A feeble signal extracting circuit with a simple structure for extracting a feeble signal such as a pilot signal. A pilot signal extracting circuit 22 comprises a band elimination filter (BEF) 30, an analog subtracter 31, an amplifier 32, and a voltage comparator 33. The band elimination filter 30 removes only the frequency components at and near 19 kHz corresponding to the pilot signal and passes the other frequency components. The analog subtracter 31 receives a stereo composite signal inputted from an FM detection circuit 18 and the signal produced by removing the pilot signal from the stereo composite signal by passing the stereo composite signal through the band elimination filter 30, outputs the differential signal of the two signals, and thus extracts only the pilot signal.
申请公布号 US2005074075(A1) 申请公布日期 2005.04.07
申请号 US20030482013 申请日期 2003.12.23
申请人 MIYAGI HIROSHI 发明人 MIYAGI HIROSHI
分类号 H04B1/16;(IPC1-7):H04L27/06 主分类号 H04B1/16
代理机构 代理人
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