SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING PIN NUMBER

摘要

A semiconductor memory apparatus capable of reducing the number of pins is provided to increase test speed by receiving address signals time-divisionally. Address pads(A0-A15) receive external address signals. Internal clock generators(170,180) generate an internal clock signal(PBCLK) in response to a first edge of an external clock signal. A first internal address generator(150) receives first address signals inputted through parts of the address pads in response to the internal clock signal before receiving an external instruction upon performing a test operation. When the external instruction is inputted, a second internal address generator(160) receives second address signals inputted through parts of the address pads. During a normal operation mode, the first internal address generator receives address signals inputted through the remaining of the address pads and the second internal address generator receives address signals inputted through parts of the address pads.