HIGH VOLTAGE CMOS DEVICE BY USING SILICON ON INSULATOR WAFER AND METHOD FOR MANUFACTURING THE SAME

摘要

A high voltage CMOS(Complementary Metal Oxide Semiconductor) device using an SOI(Silicon-On-Insulator) wafer and a fabricating method thereof are provided to drive a gate at a high voltage and reduce a chip area by improving local unevenness of a gate oxide layer. An oxide layer(104) is formed on a silicon wafer(102). A silicon substrate is formed on the oxide layer. A predetermined silicon layer(120) is formed by performing an STI(Shallow Trench Isolation) photo/etch process. An edge of the silicon layer is rounded by performing an HTHA(High Temperature H2 Annealing) process on the silicon layer. A gate oxide layer(122) is formed on the silicon layer. A gate polysilicon(124) is formed on the gate oxide layer.