发明名称 Reset control system and method
摘要 An OR circuit (34, 35) OR-operates an emulator reset signal (106, 107) based on a reset instruction from an emulator (30) and an external reset signal (115, 116) supplied from an external reset generation circuit. The OR operation result is distributed and supplied to a processor (10) and a companion chip (20) as a system reset signal (109, 110), thereby initializing both chips of the processor (10) and the companion chip (20) in accordance with the reset instruction from the emulator (30).
申请公布号 US6877112(B1) 申请公布日期 2005.04.05
申请号 US20000678733 申请日期 2000.10.04
申请人 FUJITSU LIMITED 发明人 IINO HIDEYUKI;UTSUMI HIROYUKI;HIROSE YOSHIO;RYU KEN
分类号 G06F11/28;G06F1/24;G06F11/00;G06F11/22;(IPC1-7):G06F11/00 主分类号 G06F11/28
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