| 摘要 |
The invention concerns a dual-mode divider counter circuit for a frequency synthesizer comprising several 1:2 dividers of asynchronous type connected in series, a phase selector block (11) interposed between two of the 1:2 dividers (10, 12) and a control block (13) for supplying control signals (S0, S1, S2) to the selector block in accordance with a selected mode. Said selector block receives four signals phase-shifted by 90° relative to one another from a first master slave divider and supplies one selected from the four phase- shifted signals. The control signals are (S0, S1, S2) are supplied to the selector block for selecting one of the four output phase-shifted signals (F2) in a specific period of division. On the basis of the control signals supplied by the control block (13) in one selected among the modes, the selector block operates a phase-switch at each period of division between two phase-shifted signals selected by each branch. The second phase-shifted signal selected is phase-advanced by 90° relative to the first phase-shifted signal.
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