发明名称 EXTERNAL SYNCHRONOUS A/D CONVERSION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an external synchronous A/D conversion circuit capable of attaining a high noise reduction effect by revising an interruption notice means to a CPU and an AD conversion procedure while the circuit configuration is made simple and inexpensive. SOLUTION: The external synchronous A/D conversion circuit is configured such that the circuit includes a synchronous control circuit 4 which informs the CPU 3 operated asynchronously with the conversion of an A/D converter 2 about an interruption attended with start of the conversion of the A/D converter 2, allows the A/D converter 2 to execute A/D conversion for a prescribed period until the end of interruption is notified by the CPU 3, allows a latch circuit 5 to tentatively latch a digital value resulting from the A/D conversion during a control operation of the synchronous control circuit 4 and the CPU 3 reads the digital value latched in the latch circuit 5 for plural number of times to carry out noise reduction arithmetic processing. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005086306(A) 申请公布日期 2005.03.31
申请号 JP20030313743 申请日期 2003.09.05
申请人 HORIBA LTD 发明人 YAMASHIRO HIDEO
分类号 H03M1/08;H03M1/12;(IPC1-7):H03M1/08 主分类号 H03M1/08
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