| 摘要 |
PROBLEM TO BE SOLVED: To obtain an automatic wiring design method capable of effectively mitigating a degree of wiring congestion of a wiring channel region surrounding a memory cell, by calculating an optimum wiring path of a functional inter-block wiring in the form of taking in a degree of freedom in a method for taking a line connection position. SOLUTION: In the automatic wiring design method, virtual terminals A, B, C, D are extended along internal wirings 5a, 7a, 7b, 7c for definition, and of respective positions A<SB>1</SB>to A<SB>NA</SB>(B<SB>1</SB>to B<SB>NB</SB>, C<SB>1</SB>to C<SB>NC</SB>, D<SB>1</SB>to D<SB>ND</SB>) on the extended virtual terminal A (B, C, D), the line connection position where an inter-functional block wiring 9 is an optimum wiring path (e.g., a shortest path) is obtained, and the internal wiring 5a (7a, 7b, 7c) is connected to the inter-functional block wiring 9 on the obtained line connection position. COPYRIGHT: (C)2005,JPO&NCIPI
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