| 摘要 |
PROBLEM TO BE SOLVED: To provide self-test architectures for implementing data column and row redundancy with a totally integrated self-test and repair capability in a random access memory (RAM), either a dynamic RAM or a static RAM. SOLUTION: The self-architectures are particularly applicable to compileable memories and to embedded RAM with microprocessor or logic chips. The self-architectures uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip. COPYRIGHT: (C)2005,JPO&NCIPI
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