发明名称 Efficient extractor for post-layout simulation on memories
摘要 Embodiments of the present invention relate to a computer-controlled method for extracting cell parasitic characteristics for netlist back-annotation in a circuit that comprises a row and column array of repeated cells. The method comprises the steps of generating parasitic and connection data for a row and a column of said cells in the arrayed circuit, duplicating the generated parasitic data for an additional row and an additional column in the arrayed circuit; synthesizing connection data for the additional row from a connected cell in that additional row; synthesizing connection data for the additional column from a connected cell in that additional column, and making the generated parasitic data and the synthesized connection data available for subsequent back-annotation of the netlist.
申请公布号 US6874132(B1) 申请公布日期 2005.03.29
申请号 US20020242343 申请日期 2002.09.11
申请人 SYNOPSYS, INC. 发明人 BHAMIDIPATY ACHYUTRAM
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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