Test circuit arrangement and method for testing a multiplicity of transistors

摘要

The invention relates to a test circuit configuration. Every gate terminal of a transistor to be tested is coupled to a gate voltage source in such a manner that the gate voltage can be measured and adjusted individually on every gate terminal. The source terminal of every transistor to be tested can be coupled to the source voltage source in such a manner that the source voltage can be measured and adjusted individually on every source terminal.